Power Aware Test Architecture for System-on-Chip

Abstract

VLSI industry is currently in the era where all electronic circuits necessary to complete the system are being fabricated on a single chip known as System-on-Chip (SoC). Today's SoC is composed of large number of Intellectual Property (IP) cores with diverse nature. With the advances in fabrication process for IC, the manufacturing cost has reduced significantly and now the testing cost is becoming a dominating part of the overall cost of an IC. The testing cost is strongly related to the increasing test-data volumes as the larger test data volume lead to longer test application times. The current methodologies for test time reduction are efficient but ever increasing test data volume needs more efficient test time reduction methodologies. Generally, the efforts for test time reduction cause the increase in test power. Excessive test power and test energy results in reliability issues, thermal issues and in some cases yield loss too. In this thesis, the major testing issue \Test Time" in context of \Test Power" is focused. From various test time reduction techniques available in literature, the techniques dealing with test frequency scaling constrained by power budget and test scheduling are selected for further research. It is very natural that as the dynamic test power is proportional to test frequency, any efforts to reduce test time by increasing test frequency, cause the increase in test power and may violate the power budget. We have considered here the dynamic scaling of frequency considering the maximum allowable test power of individual core and maximum allowable test power of entire SoC. In this thesis, we have proposed two methods: 1. Dynamic-Test-Frequency- Allocation to IP Cores of SoC (DTFA Cores) 2. Dynamic- Test-Frequency-Allocation to Test Vectors of IP Cores (DTFA Vectors). In DTFA Cores, we have reduced the test time of individual core by Dynamic Test Frequency Allocation to different Cores under the constraints of power budget of individual core. Here we are increasing or decreasing the test frequency of core based on power budget of Core and overall power budget of SoC. Further, we are applying here Integer Linear Programming for test scheduling of cores of SoC under constraints of power budget of SoC. In DTFA Vectors, we have applied the increase in test frequency to individual test vector which in turn reduces the scan-out & Scan-in time of test vector pair. Based on the number of transition during scan-vector pair, the frequency is up scaled under the constraint of rated average power of core. This method requires the on-chip Dynamic Test Frequency Generator (DTFG). The DTFG converts the rated test clock frequency to dynamic clock frequency. Further, as the frequency is changing at core-to-core or vector-to-vector, the test pattern is prefixed with frequency indicator. For both proposed methods, we have shown the experimental results on widely used ISCAS benchmark circuits and ITC benchmark SoCs. We have included the results for session-less and session-based test scheduling in case of Bus-based-SoC as well as NoC-based-SoC. The proposed methods cause a small bit overhead. So such frequency allocation scheme is evaluated on the basis of its test time reduction capability, on-chip area overhead and on-chip bit overhead (of course, the power budget should not be crossed in any case). Effectiveness of these methods are demonstrated with large amount of simulation results. The experimental results prove the effectiveness of proposed method compared to recent methods in literature.