Register Verification Tool and Coverages for RTL Design

Abstract

the complexity nature of Very Large Scale Integrated (VLSI) designs increments, so does the expense of testing VLSI products. VLSI testing must be practical to address the difficulties of technological progression. As the requirements of the design increases according to the customer’s specification the complexity of design also increases. To make the architecture bug free efficient and reliable tools must be designed for verification. High level verification is required to verify each aspect of the design. Coverages play an important role to analyze a RTL design. It is utilized as a security net to guarantee that the verification plan was as finished and that the plan was checked as completely as could reasonably be expected. It helps to understand the quality of the design and detect where there can be faults. Coverage is important to test whether all the test plans are tested and verified. Code coverage and functional coverages are already used in the industry. To minimize or remove the limitation of these coverages a more advanced coverage is designed which works by continuous regressions on an RTL. This method is called statistical coverage which helps to identify weakness in a test case. Another aspect which is required for verification is proper form in which the design of the model can read and understood by the customer. Also, it is very necessary that before conducting any test to verify a register model that the model should have met all the requirements. Sometime due to lack of proper representation of the design can lead to irregularities or duplication of data. This may lead to appearance of bugs in the architecture model. Hence it is required to have machine readable specification of these models. For the generation of these specification a tool or algorithm is required as manual work can be very tedious and time consuming. UVMreg model is used for this purpose which helps to ease the verification process by generating Machine readable specifications. Another type of coverage for verification is functional coverage .It provides details of what part of the device under test are working. A related but distinct concept is code coverage. In code coverage, each line in a program is marked as "hit" if it is executed at least once and "missed" if the line was never executed. Rather than tracking what lines in a program have hit, functional coverage tracks what values a signal have hit. Also like code coverage, functional coverage for a given signal can be expressed as a percentage. If a 2-bit signal only attained values {00, 01, and 11} over the course of a simulation, then this signal has reached 75% coverage for that simulation.A test generator and memory checker tool is used for multi level verification. It is designed to check the presence of specific architecture scenarios. Includes simple coverage on instruction encodings, system register space, and cross coverage.