Validation of SoC Design using Hardware Emulator

Abstract

As the complex nature of Very Large Scale Integrated (VLSI) designs increments, so does the expense of testing VLSI products. VLSI testing must be practical to address the difficulties of technological progression. As the requirements of the design increase according to the customer’s specification the complexity of the design also increases. To make the architecture bug free efficient and reliable tools must be designed for verification and validation. High-level verification and validation are required to verify each aspect of the design. Hardware Emulation plays an important role to analyze an RTL design. It is utilized as a security net to guarantee that the verification plan was as finished and that the plan was checked as completely as could reasonably be expected. It helps to understand the quality of the design and detect where there can be faults. Hardware Emulation is important to test whether all the components and IPs are tested and validated. The main purpose of hardware emulation is to validation the whole design. In that different IPs are integrated and combine and made a full SoC. To check full SoC whether there is a bug or not after the integration of multiple IPs then hardware emulation plays a major role in validating the SoC. Another aspect that is required for validation is the proper form in which the design of the model can be read and understood by the customer. Also, it is very necessary that before conducting any test to verify a register model that the model should have met all the requirements. Sometimes due to lack of proper representation of the design can lead to irregularities or duplication of data. This may lead to the appearance of bugs in the architecture model. Hence it is required to have the machine-readable specification of these models. For the generation of these specifications, a tool or algorithm is required as manual work can be very tedious and time-consuming. PythonSv is used for this purpose which helps to ease the validation process by generating Machine-readable specifications and it can be used for the reading and writing of the different IPs register.