Impact of Macro Placement on Design QoR in Physical Design

Abstract

As the complexity of SoC design and its fabrication is increasing with the modern technology node, it is necessary to invest more efforts in various physical design stages like floor planning, placement and routing. The increase in the number of transistors per chip comes with so many challenges at design, technology and tools. Hence, the process of designing any circuit becomes more complex which requires optimization and automation. Nowadays, EDA tools are used for the design and fabrication of electronic systems like ICs.

The process of converting a circuit representation of the design into physical layout is known as physical design which describes the cell placement, floor planning and routing for communication between them. All the semi-conductor giants follow the basic physical design flow to meet various criteria like power, performance and area. To meet these criteria, SoC contains more macros which creates the necessity of good macro placement techniques. Macro placement is done at a floor planning stage of physical design. There are so many approaches used for the macro placement. These approaches are dependent upon the pin orientation, connection between two macros and connection with I/O pins/pads. Generally, macros are placed around the chip boundaries in the core area so that the connection with pins can be easy. It won’t be feasible every time as the numbers of macros will differ. It can be placed manually or automatically which is decided by number of macros. If the number is less, then they can be placed manually. The main goal is to check the impact of different placement approaches in terms of power, performance and area.

This project consists of various placement approaches and guidelines which are followed during the macro placement. The idea of this project is to show the impact of macro placement on design QoR and to optimize the timing and routabilty constraints through macro placement. It helps the designers to observe the basic guidelines used to obtain better results in terms of routability, wirelength and timing. Additionally, this proposal can be used for evaluating the congestion according to the location of I/O pin, dimension of macros and impact of them.