Impact of Physical Cell Placement on Physical Design Flow

Abstract

The complexity of SoC design and its fabrication is increasing due to the decrease in size of technology node . Hence more efforts should be given into doing physical design of these SoC. Many challenges have arisen in terms of design, technology and tools as the number of transistors per chip are increasing. Hence, optimization and automation of the circuits have also become complex. To deal with these problems EDA tools such as Fusion Compiler, Innovus, IC compiler II, etc are used. The process of converting a circuit representation of the design into physical layout is known as physical design, which describes the cell placement, floor planning and routing for communication between cells and macros. All the semiconductor giants follow the basic physical design flow to meet various criteria like power, performance and area. Physical cell is one of the parts of these constraints. The main aim of this project is to get detailed review of the impacts of different physical cells. By adding physical cells to the design, changes occur in terms of power, area and performance. To study these impacts Fusion Compiler is used as a tool. Impact of tap cells, end-cap cells, filler cells and de-cap cells are studied.

For any physical cell it is important to be placed in correct orientation otherwise it leads to an increase in the number of DRC values. This increase occurs due to change in position of vts_n which leads to n-well discontinuity. Other impacts such as area and power are studied for these physical cells. For tap cells, it is seen that there is an increase in the number of DRC around 3.35% as we decrease the number of well-tap cells used within the design. Similar changes occur for filler cell, de-cap cell and end-cap cell with respect to DRC count. Mainly in tap-cell and filler cells, DRC occurs due to n-well discontinuity. For de-cap cells, there is decrease in dynamic power when decap cells are increased but after a certain number of increase in de-cap cells, dynamic power also increases. Hence, the dynamic power increase or decrease depends on the number of de-cap cells used within the design. The study also helps us to realize that if physical cells are absent within the design then there would be degradation in the quality of the chip.