SAGE ATPG Flow for Xeon Server SoC

Abstract

The chip manufacturing process is susceptible to defects. These defects are increasing in numbers as we are going into lower manufacturing process. When these defects are mapped into the silicon, we commonly refer them as faults. All these faults will be testable and hence detectable if we use a well-specified technique. To test these faults we add additional logic, this logic is called Design For Testability (DFT). DFT is the internal modification of the circuitry to increase the observability and controllability. We test these silicon chips by giving the test patterns as an input and comparing the resultant output without reference model. To generate these patterns, we use the technique called ATPG (Automatic Test Pattern Generation). SAGE flow is used for ATPG generation. SAGE stands for Scan Automatic pattern Generation and validation Environment. This flow many steps staring from ATPG_CONFIG_GEN to ITPP_GLS. This project report contains the detailed information of the steps and of the test architecture.