Synthesis and STA Design of Synopsys Foundation IPs

Abstract

-day System-on-Chip(SoC) are becoming more and more complex due to more transistors are packed per unit area of the chip. SoC contains multiple IPs which are integrated. Present-day technologies like Artificial Intelligence(AI), Internet-of-Things(IoT), wearable gadgets, handheld devices like smartphone & tablets, etc are memory-hungry devices which use the Embedded Memory IP. There is a need that Memory IP and Embedded Test and Repair IP to work at their best in the SoC for lower technology nodes. Synopsys Application Engineering(AE) Team working in the area of Foundation IP used to help the customer across the globe to use the Foundation IP in their SoC. Failure of these IPs after integrating into the customer’s SoC can delay the time-to-market window for the customer. Doing the complete Application Specific Integrated Circuit(ASIC) Flow will help the AE to better understand the problem faced by the customer and to come up with more innovative solutions. Synthesis is the process of converting RTL code into a technology-dependent optimized gate-level netlist. After Integrating IP, Timing constraints have been written as per the specification. Block-level Synthesis has been performed using Synopsys Design Compiler tool using its various optimization technique for achieving better timing, power, and area. Static Timing Analysis (STA) is the technique to analyze the timing violation and fix the violation using Engineering Change Order (ECO). STA has been performed using the Synopsys Prime Time tool. Setup, Hold, Removal, and Recovery checks have been performed and fixed using various techniques to operate the design at optimum speed.