Physical Design Implementation with Low Power

Abstract

In the present scenario, the VLSI industries are on the verge of reaching the maximum limit of CMOS scaling to sustain Moore’s law. Reducing the CMOS device size plays a very crucial role in the VLSI sector when prioritized aspects such as IC integration or, low power design, and high-speed circuits or high operating frequencies is the need of current period and will remain in the future. DSP block is based on wireless application and consists of arithmetic-intensive algorithms. As wireless devices rely on battery for their functioning, there is limited battery power available for a system to work. In addition, as the device area decreases and complexity or functionality of the device increases, there is high power consumption by chip.

Increased device scaling has lead to higher static (leakage) power, high frequency logics have lead to higher dynamic(switching) power. This sums to higher power dissipation in the design. To overcome such higher power dissipation, various low power techniques are applied, where such dissipation can be controlled. Also, as the devices are getting shrinked, there are more functionalities/logics getting implemented, which leads to increase in area of design, Thus, various utilization techniques are involved to get the optimized area for the logic to be placed in the design.

In this project, PnR activity primarily focuses on reducing the power consumption, optimizing the area utilisation and closing timing and drc violations for the DSP block. The block is a multi power domain system and have three power states. Various challenges are faced in terms of congestion and timing violations trading off with placement density and power consumed. Different experiments and techniques were implemented to improve results.