Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/10517
Full metadata record
DC FieldValueLanguage
dc.contributor.authorDadlani, Hitesh-
dc.date.accessioned2022-01-21T11:56:57Z-
dc.date.available2022-01-21T11:56:57Z-
dc.date.issued2021-06-01-
dc.identifier.urihttp://10.1.7.192:80/jspui/handle/123456789/10517-
dc.description.abstractThe EDA industry has evolved rapidly over the last two decades. Designer’s productivity has raised due to improved EDA tools over the last quarter of the century. Moore’s law was made more effective and efficient with help of EDA tools. EDA tools have become essential in the design of chips with high complexity. The first integrated chips were small-scale integration chips where the gate count was very small. With the advancement of technology, designers were able to place circuits with thousands of gates on a chip. As the number of gate counts increased design process started getting complex, designers felt the need to automate the process. Developers moved to the development of EDA tools in the design flow. The development of EDA tools in design flow depends on four major interrelated principles. The four principles on which EDA tools are developed are modularity, integrity, operate incrementally, have less runtime. This Project introduces automated flow for front-end tools which eased the process of front-end tools execution. In the front-end domain, there are nearly forty tool flows. This project covers the various static flows used in the front-end domain. The automated flow will manage dependencies between these flows for serial & parallel execution depending on the input file. The automated flow comes with many features that can reduce the execution time and engineering efforts. The features include the dependency stage, different modes of execution, simple input format for the project, and tool configurations. The developed automated flow supports the standard environment used for INTEL projects. The automated flow is developed using PERL. Regression Testing is done to ensure the tool meets the required quality goals.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries19MECV06;-
dc.subjectEC 2019en_US
dc.subjectProject Report 2019en_US
dc.subjectEC Project Reporten_US
dc.subjectEC (VLSI)en_US
dc.subjectVLSIen_US
dc.subjectVLSI 2019en_US
dc.subject19MECen_US
dc.subject19MECVen_US
dc.subject19MECV06en_US
dc.titleAutomated Flow to Manage Dependencies between Different Flows – Serial & Parallel Execution of Design Stepsen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, EC (VLSI)

Files in This Item:
File Description SizeFormat 
19MECV06.pdf19MECV06728.5 kBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.