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DC Field | Value | Language |
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dc.contributor.author | Dadlani, Hitesh | - |
dc.date.accessioned | 2022-01-21T11:56:57Z | - |
dc.date.available | 2022-01-21T11:56:57Z | - |
dc.date.issued | 2021-06-01 | - |
dc.identifier.uri | http://10.1.7.192:80/jspui/handle/123456789/10517 | - |
dc.description.abstract | The EDA industry has evolved rapidly over the last two decades. Designer’s productivity has raised due to improved EDA tools over the last quarter of the century. Moore’s law was made more effective and efficient with help of EDA tools. EDA tools have become essential in the design of chips with high complexity. The first integrated chips were small-scale integration chips where the gate count was very small. With the advancement of technology, designers were able to place circuits with thousands of gates on a chip. As the number of gate counts increased design process started getting complex, designers felt the need to automate the process. Developers moved to the development of EDA tools in the design flow. The development of EDA tools in design flow depends on four major interrelated principles. The four principles on which EDA tools are developed are modularity, integrity, operate incrementally, have less runtime. This Project introduces automated flow for front-end tools which eased the process of front-end tools execution. In the front-end domain, there are nearly forty tool flows. This project covers the various static flows used in the front-end domain. The automated flow will manage dependencies between these flows for serial & parallel execution depending on the input file. The automated flow comes with many features that can reduce the execution time and engineering efforts. The features include the dependency stage, different modes of execution, simple input format for the project, and tool configurations. The developed automated flow supports the standard environment used for INTEL projects. The automated flow is developed using PERL. Regression Testing is done to ensure the tool meets the required quality goals. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 19MECV06; | - |
dc.subject | EC 2019 | en_US |
dc.subject | Project Report 2019 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | EC (VLSI) | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2019 | en_US |
dc.subject | 19MEC | en_US |
dc.subject | 19MECV | en_US |
dc.subject | 19MECV06 | en_US |
dc.title | Automated Flow to Manage Dependencies between Different Flows – Serial & Parallel Execution of Design Steps | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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19MECV06.pdf | 19MECV06 | 728.5 kB | Adobe PDF | ![]() View/Open |
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