Automation on Routing optimization for VLSI Physical Design

Abstract

The VLSI design of the circuits is becoming very challenging day by day and that is because of interconnecting delay of the routing. As per research Buffer insertion, wire width, and proper space between the two metal wires in VLSI physical routing is a very essential and very useful thing in multi constrain optimization problem. In global routing, the multi contains are mainly power, delay, and area.

The focus of the project is to reduce the interconnect RC delay for timing critical delay by applying different techniques on that net. Multiple solutions can be applied for a reduction in interconnect delay reduction such as widening, spacing, shielding of that routing but the main important techniques are topology and repeater insertion at the required place.

The Automation which is used in this project is to find the optimum solution with the help of different techniques like widening, topology change, and buffer insertion without crating space and short DRC violations in the routing area. The Simulation results showing that the proposed automation technique can solve the RC delay requirement for the timing critical routings and handles the multiple constraints. In this project developed scripts are in TCL language.

This thesis covers various techniques of routing optimization like fixing timing critical nets and solving DRCs. By these methods there are significant improvement can be noticed by the results. And the overall manual efforts can be reduced up to at least 50-60 %.