Pre-Silicon Scan Validation and Pattern Transformation

Abstract

As the transistor size reduces, we can accommodate more complex logic in very small chip. Testing of such a small chip is a challenging task. Today testing of the chip takes around 30% to 50% of the total product cost. Test techniques have become crucial part in success of the product in marketplace. Design for testability is a technique used to detect the manufacturing defects using test generation and test application. Test generation is accomplished by Automatic test pattern generation using fault models and algorithms. Test generation for sequential circuits is difficult due to poor initializibilty, controllability and observability of the circuit. Scan design is one of the most widely used approach for improving the intializibility, controllability and observability of the circuit by converting the storage element in the circuit into combination of the mux and flipflop. This way sequential circuit becomes virtual combinational circuit, for which combinational ATPG can be used for test pattern generation. In this work, Scan validation architecture has been explored. RTL based scan validation strategy is useful in detecting faults in the early stages of the cycle. Pattern transformation for converting the block level test pattern into full chip level pattern has been discussed in the later part. After that, as part of Scan validation, Evil validation is introduced, where the effect of corrupted scan cell is analyzed over the critical signals of the systems like powergoods,clock signals etc.