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DC Field | Value | Language |
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dc.contributor.author | Kevat, Pooja | - |
dc.date.accessioned | 2022-01-25T06:12:48Z | - |
dc.date.available | 2022-01-25T06:12:48Z | - |
dc.date.issued | 2021-06-01 | - |
dc.identifier.uri | http://10.1.7.192:80/jspui/handle/123456789/10526 | - |
dc.description.abstract | VLSI is a engineering related to design, verification and physical implementation of Integrated circuits. It has been growing since invention of first integrated circuit. As technology advanced, it became possible to reduce device dimentions. With that more and more devices were possible to be fabricated on single IC. Due to its’ requirements in communication devices and computing devices, research on IC went on to improve performance. Today IC have dimension in nanometers and research on better devices is going on. This have improved area performance but increased design complexity. As area of components reduced, the routing requirement for devices per area also increased. This tradeoff limits performance of IC. It needs tradeoff between three performance parameters: power, area and performance. ASIC is application specific chip and is designed and optimized for given technology node and requirements from architecture. RISC-V architecture is developed and preserved as open architecture. Many people are contributing to this effort. This architecture is designed by keeping in mind all the performance parameters, especially power consumption. Physical design engineers converts architecture/ logic design into final IC. As technology is shrinking, physical design is becoming increasingly challenging. Design Rule Manuals are used to implement design optimally. These rules are becoming complex as technology node is shrinking. Improving all performance parameters- power, timing and area is challenging. Many experiments are done on single node single block design before getting perfect violation free output. Reducing runtime of PnR processes is one of the issues to be resolved. Single error can waste a lot of human working hours. Using tool smartly is also one of the skill an engineer can possess. Deep understanding of input timing constraints is required. Wrong input causes flawed output with correct process. Understanding of design is necessary, understanding critical paths is half the solution for issues faced. To approach design with generic point of view helps a lot. If we understand every process and have knowledge of undetected issues in one process that can affect another process, it is easier to resolve issues. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 19MECV09; | - |
dc.subject | EC 2019 | en_US |
dc.subject | Project Report 2019 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | EC (VLSI) | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2019 | en_US |
dc.subject | 19MEC | en_US |
dc.subject | 19MECV | en_US |
dc.subject | 19MECV09 | en_US |
dc.title | Physical Design of ASIC Block in 12nm Technology | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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19MECV09.pdf | 19MECV09 | 1.87 MB | Adobe PDF | ![]() View/Open |
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