RC Delay Reduction Methods for Routing Optimization

Abstract

Today’s ASIC design having deep-submicron processes and for this type of technology node layout had a very important role to play. Routing is becoming very challenging with each technology node due to the increasing number of metal layers and design complexity. To transmit signals from one end to the other end as fast as possible, while minimizing losses, is critical in sub-micron technology. At a nanometre scale, routability has become one of the most critical problems in back-end design.

Generally, the frequency at which the signal propagates in a circuit is determined by the resistance and capacitance of the metal wires used in the interconnection of the transistors. The product of resistance and capacitance is called the RC delay of the wire.

In this project, various techniques to reduce RC delay are addressed. This thesis covers the methods to reduce the resistance and capacitance by changing different parameters of wires such as width, metal layer and spacing between two nearby wires. Other methods involve the insertion of some extra wires or repeaters to improve the timing performance. The application of available methods requires human efforts to solve the RC delay problem. The main objective of this project is to automate the process of application of these available techniques of reducing RC delay. This thesis presents an automation flow for the implementation of different methods using TCL scripting language.

The results show that there is a significant improvement in the timing of the wire after applying these methods. And with the help of automation, overall human efforts and time are saved by implementing scripts.