Power Reduction and Area Optimization in Physical Design Implementation of a DSP Block

Abstract

In the present scenario, the VLSI industries are on the verge of reaching the maximum limit of CMOS scaling to sustain Moore’s law. Reducing the CMOS device size plays a very crucial role in the VLSI sector when prioritized aspects such as IC integration or, low power design, and high-speed circuits or high operating frequencies is the need of the current period and will remain in the future. DSP block is based on wireless applications and consists of arithmetic-intensive algorithms. As wireless devices rely on battery for their functioning, there is limited battery power available for a system to work. In addition, as the device area decreases and complexity or functionality of the device increases, there is high power consumption by chip. Increased device scaling has led to higher static(leakage) power and high frequency logics have led to higher dynamic(switching) power. This sums to high power dissipation in the design. To overcome such high power dissipation, various low power techniques are applied, where such dissipation can be controlled. Also, as the devices are getting shrinked, there are more functionalities/logics getting implemented, which leads to an increase in area of design. Thus, various utilization techniques are involved to get the optimized area for the logic to be placed in the design. In this project, PnR activity primarily focuses on reducing the power consumption, optimizing the area utilization, to close the timing and logical/low-power/physical verification checks for the DSP block. The block is a multi-power domain system and has three power states. Various challenges are faced in terms of congestion and timing violations trading off with placement density and power consumed at every PnR stage. Different experiments and techniques were implemented to improve the overall results. The implementation of low power intent information and other PnR aspects in the block has been discussed. There are other techniques described such as VT type cell distribution and clock tree optimization which impacts the timing, area and power aspects of the design. On logical/low-power/physical verification checks of the block such as LEC, CLP, DRC and LVS checks, the reported violations and the methods to fix those violations are discussed in the last section in order to close the block meeting the sign off criteria.