SoC Front-End Integration Flow.

Abstract

There are number of cores to be integrated in an SoC. and these cores should be connected with highest level of accuracy. If any of the connection is missed and not caught by verification test case, it will result in the post silicon bug and that will the full design re-spin and design re-spin costs a lot in terms of money and time. As I mentioned earlier an SoC contains top level connections in the multiple of 10's of thousands. So, connecting each wire separately is tedious job and each connection should be tested for Lint issues like multi-driver issues and signals with no driver issued at both top-level connectivity as well as entire SoC level which must be detected from when the design is not that mature. Ill also bring you to an important aspect creating link between front end design(RTL) and how RTL will look after it is arranged as per the layout(Tiled RTL). The whole idea behind this project is to show one of a way to manage connectivity accurately with some ease with some level of automation. I will also explain step by step process for SoC Integration. Also, we will see some level of automation as a part needed for executions of Integration flow. We will also use some custom scripts which are necessary to be used in order to save time and efforts.