Static Timing Analysis of a block for better Power, Performance and Area.

Abstract

Timing analysis is an important step in the VLSI design flow. It helps in validating if the design can operate at the rated speed. The chip must not only meet the functionality requirements, but also the timing requirements. Static timing analysis is a technique to exhaustively verify the timing of a design. This type of analysis performs timing checks for all the possible paths and scenarios of a design. It checks for all the timing violations without any need of applying data vectors at input pin. Thus, STA is a faster and efficient technique for verifying the timing.

In the project work, Timing runs in the flow is carried out. In those STA runs, in the initial stage of a project various critical corners are included. These critical corners depends on the project we are working on. And later other corners are added as per requirement, for the exhaustive timing verification across all the possible scenarios i.e.when the chip is working in real time. STA checks include setup, hold and Timing DRCs like maximum capacitance, maximum data and clock transitions, minimum period, minimum pulse width. Also, other checks like clock duty cycle distortions, recovery and removal time. Once the timing runs are completed, reports are dumped out and analysed thoroughly. Based on that setup, hold, Timing DRCs fixes of those violating paths are done using various techniques. Some of those techniques are Upsizing the cell, adding buffers in the path, breaking the net, swapping of the threshold voltage levels and so on depending on the type of violation.