Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/10533
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shah, Bhasha M | - |
dc.date.accessioned | 2022-01-25T06:53:32Z | - |
dc.date.available | 2022-01-25T06:53:32Z | - |
dc.date.issued | 2021-06-01 | - |
dc.identifier.uri | http://10.1.7.192:80/jspui/handle/123456789/10533 | - |
dc.description.abstract | The rapid demand of high performance and high-speed VLSI systems has shifted the focus of technocrats from traditional performance parameters like area and speed towards the analysis of power consumption and optimization. Hence the power budget and management among the domains of the system is very much essential in ICs designed today. Addressing dynamic leakage power requires new techniques and standards that fall outside the scope of traditional HDL-based flows. Implementing such low power techniques at the RTL creates new design and verification challenges. Unified Power Format (UPF) is an IEEE standard 1801-2018 that allows designers to describe low power design intent and improve the way complex integrated circuits can be designed, verified, and implemented. VC LP is a multi-voltage, static low power rule checker Synopsys Tool which will verify low power management techniques and UPF intended challenges like management of power domains activity, control signals and supply rails availability and retention of previous data for functional correctness in the design. Further, UPF is used to describe the power intent with low power elements like Isolation Cell, Level Shifter Cell, Power Switches and Retention Cell. Thus, VC LP will enable UPF to verify static low power checks at early design cycle. This thesis covers power management concepts of UPF and Static Low Power Checks of the design. Sign-off Checks is done at the Synthesis and Place & Route stage of physical implementation for further acceptance in the chip flow. The main aim of the project is to simplify or develop an automated Engineering Change Order (ECO) for the efficient analysis of the output reports and to reduce the runtime of the tool. The two prominent scenarios of VCLP i.e., Wrong Domain Buffering and Level Shifter Insertion has been taken care of, with the consideration of all corner cases. And finally, after the identification of the intended instances the feedback ECO file will be provided as an output of the TCL script. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 19MECV16; | - |
dc.subject | EC 2019 | en_US |
dc.subject | Project Report 2019 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | EC (VLSI) | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2019 | en_US |
dc.subject | 19MEC | en_US |
dc.subject | 19MECV | en_US |
dc.subject | 19MECV16 | en_US |
dc.title | Low Power Sign-Off Checks and their Efficient Engineering Change Order (ECO) Implementation | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
19MECV16.pdf | 19MECV16 | 1.8 MB | Adobe PDF | ![]() View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.