Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/10534
Title: | SoC Quality Checker Tool for Pre-Silicon Verification |
Authors: | Srivastav, Shubham |
Keywords: | EC 2019 Project Report 2019 EC Project Report EC (VLSI) VLSI VLSI 2019 19MEC 19MECV 19MECV17 |
Issue Date: | 1-Jun-2021 |
Publisher: | Institute of Technology |
Series/Report no.: | 19MECV17; |
Abstract: | Pre-silicon verification is typically performed at the multichip, chip, or device level. The main purpose of pre-silicon validation is to check the design’s accuracy and sufficiency. The design model being evaluated may be RTL whereas this method involves modeling of the entire system, and other system components may be functional models of behavior or bus. The exponential increase in the number of the gate in modern integrated system which combines the use of IP cores and reuse of methodologies and advancements in design leads to more complex, larger, and highly integrated designs. The goal is to subject the DUT (design under test) to input stimuli similar to real-world stimuli. The increase in complexity of integration requires much time and effort in checking and verifying the quality. The proficiency of an IP should be assured properly before handling out the entire concept to the SoC team. To determine the accuracy and reduce in run round time of manual testing, we need to automate the process. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/10534 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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19MECV17.pdf | 19MECV17 | 691.07 kB | Adobe PDF | ![]() View/Open |
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