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http://10.1.7.192:80/jspui/handle/123456789/10535
Title: | Automating Scan ATPG Regression for SoC |
Authors: | Thobhani, Parth Kishorbhai |
Keywords: | EC 2019 Project Report 2019 EC Project Report EC (VLSI) VLSI VLSI 2019 19MEC 19MECV 19MECV18 |
Issue Date: | 1-Jun-2021 |
Publisher: | Institute of Technology |
Series/Report no.: | 19MECV18; |
Abstract: | As the technology node reduces, the device becomes faster, and the complexity of the chip increases. The reduction in feature size increases the probability of manufacturing defects in an Integrated Circuit. Thus, it is significant to test the IC once they are taped out. To address the testing challenges for the physical defects, DFT (Design for Test) architecture has become popular in the industry. DFT majorly involves the task to convert flops into muxed flops and connecting each flop (chains) to make the internal nodes of the design more controllable and observable. Thus, to make the design more testable. Scan inserted netlist will be given to the Test pattern generation tool (ATPG tool). A System on Chip IC becomes famous nowadays that integrates most components of a computer or other electronic system. Each SoC has multiple partitions or fubs or blocks as per its functionality. Before targeting the full SoC for pattern generation first we need to ensure the pattern generation and its simulation of all partitions of the SoC. Then we can target specific regions for ATPG. Each region contains some 2-3 or more partitions. Partition level ATPG has the most common processes between them. To save the execution time of pattern generation, we want to run the most common processes of all available partitions of the SoC in a parallel manner. This helps us to speed up our execution time and easy debugging. This project discusses the scan ATPG Generation flow and automation of ATPG regression run for SoC partitions. It majorly covers enablement of setup at pre-hook so that we can run atpg for all partitions parallelly. It covers necessary reports generation (scan xml generation) for mapping the flop information in the netlist to RTL for all scan chains to help at various stages before manufacturing. It covers the approach for coverage analysis and debug failed simulation of generated patterns. TCL script is developed to fetch total faults data, atpg status, and simulation status by using coverage statistics reports and available log files. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/10535 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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19MECV18.pdf | 19MECV18 | 1.08 MB | Adobe PDF | ![]() View/Open |
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