Standard Cell Characterization

Abstract

Present-day VLSI design implementation flows are based on cell libraries. The standard cell library is the basic and important building block in IC design. Standard cell libraries are nothing but a bunch of basic cells with different functionality, size, and strengths. Standard cells are pre-design and pre-characterized. Cell design flow starts with a PDK (Process Design Kit). Foundry provides PDKs to the designer community for a certain technology node. By using PDKs, the designer community models transistor, capacitors, diodes, resistors, and other components. Designers use the truth table or Boolean equation and start cell designing with transistor netlist as the schematic. After that, the cell layout is created, and several checks (DRC) are performed, and cell requirements are validated. The last step in the cell design flow is characterization. Characterization of cell uses a technology model, extracted netlist from layout view, a circuit simulator (like ELDO), and characterization software. Using all these inputs, the characterization tool generates noise, timing, and power models. These models are consolidated in the form of the library (in Synopsys Technology Format) along with some important views and documentation in form of a package. These packages are used by different tools in digital analysis and implementation flow. This thesis contains information about different cells and files used in VLSI design. Later, it introduces industry techniques and methods for characterization and model generation.