I/O Performance Validation

Abstract

Post silicon certification is an important process for chip production. Large semiconductor companies have spent millions of dollars on manufacturing electrical components. Verification includes various functions such as operational accuracy, power adherence and performance barriers in targeted environments, tolerance of electrical noise genes, security guarantees, resilience against physical stress or thermal problems in the area, and so on. Due to the increased complexity of SoC design coupled with reduced market time constraints, it is not possible to detect all design errors during pre-silicon verification. The modern processors have complex software systems subject to numerous non-functional requirements. The meaning of performance validation is to measure Bandwidth and Latency at various power levels. With a multi-cores processor and complex structures, ensuring content performance with other key IPs becomes a very important task. The Peripheral component interconnect express (PCIe) is a highly efficient and widely accepted connectivity component in the computer industry, and is one of the most complex areas of HSIO. PCIe performance verification is important as data rates rise throughout the new generation. This thesis contains the working of PCIe and approach for PCIe IO validation testcases as part of post silicon validation.