VLSI Design on GPIO

Abstract

The physical design on the GPIO partition is a part of the full chip design. The backend design of a commercial chip includes many privacy and compliance issues. Due to which the Place and Route was conducted parallelly on the traffic signal Verilog file whose im ages are presented in this document. The project involves detailed steps of the placement and route on hard IPs and standard cells. Many critical issues are looked upon that determine the quality of the chip. The power performance of the chip was taken into account and technique was developed to reduce power loss in the design. The timing checks were performed in different corners and the experiments were performed to achieve the target slack. The network latency and around the chip timing are investigated since GPIO acts as an input and output port to the entire chip. Different signoff checks are looked into such as VCLP, FEV, and the design mismatches are identified and solved. The constant feedback and suggestions from different teams such as RTL, RV, LV teams are discussed constantly to arrive at a best-in-class chip. The rigorous study of the Fusion Compiler tool User guide. Many tool-related industry videos, flow videos, and readings were performed before the performance of the project. The sample project was performed to optimize the power consumption of the chip and automate the power usage power utilization techniques to suit the 3 defining parameters of Power, Performance and Area which are documented in the report.