Verification of Shared Memory Architecture

Abstract

Shared memory architecture used in most of modern computer technology. So, data from the same memory location can be shared by multiple processors. And it’s a must to maintain the memory consistency and coherent nature through the shared memory model. So in situations like multiple write an operation and data sharing, an updated copy of the data should be visible to every processor. Some protocols are helpful to ensure the cache coherency in a multiprocessor system. The goal of the project is to verify consistency and coherence methodologies implemented in the design at SoC level. We seen the complexity of digital devices and time limitations on complete manufacturing flow. So, it’s a challenging task to ensure the efficiency of design flow with respect to time limitations. More focus is placed on functional validation in order to complete the highly complex system in short time. Two important aspects of today’s functional verification are quality and re-usability. In the design development cycle complexity of design, time to market rate and efforts of bug fixing are factors dependent on each other. Increasing design complexity, shrinking time to market, and high cost of fixing a bug in a released product make functional validation of IP is important in the product development cycle. This thesis describes the steps carried out to reuse an already existing VAL environment for SoC verification. Steps carried out are testbench cleanup, implementation of test run methodology. Testbench cleanup involved updating of design parameters, library dependencies and code clean up. For test run methodology implementation, activities involved like compile cleanup, updating configurations and dependencies in system design environment. In second stage, adapting the new test run methodology with existing one was the main goal. In third stage we checked the functionality of existing design by running some individual and regression lists. Also new and existing test run methodology verified on the existing design. In the fourth stage we integrated some VAL modifications at SOC level with respect to the architecture changes done in the design. In the fifth stage, to observe the actual results and functionality of shared memory architecture we run the test with .asm file attachment. After loading the traffic to memory, we will ensure the RTL functionality through logs and results.