Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/11274
Title: Crosstalk Noise Reduction Method in Physical Design
Authors: Singh, Karan
Keywords: EC 2020
Project Report 2020
EC Project Report
EC (VLSI)
VLSI
VLSI 2020
20MEC
20MECV
20MECV06
Issue Date: 1-Jun-2022
Publisher: Institute of Technology
Series/Report no.: 20MECV06;
Abstract: When we go through the chip design cycle, there are three thing that we try to achieve on chip. (a) Power, we always look for low power consumption on chip if we take an example of cell phone, everyone needs good battery life. As lower the power consumption in chip higher the battery life. (b) Performance, we all want to run a greater number of program at a time without compromise with the speed. The Good performance chips also be the priority. (c) Area, we all need better form factor in modern day devices without compromise with performance. Also, from industry point of view, Area plays a key role. We need to use area very efficiently to fulfill the market need. The all three aspect always be on top priority of any chip designer but the phenomenon of crosstalk is the one who can hamper all three-power performance, and area in that manner that it could be very difficult to recover them. As we know, technology node shrinking very rapidly and due to this the crosstalk issue become one of the biggest challenges for chip designers. In this project thesis, we will discuss the mains reasons of occurrence of crosstalk Noise and some effective reduction method like shielding, upgradation of metal layers and element insertion method. The results will show that there is a significant improvement after applying these methods. And with the help of automation, overall human efforts and time are saved by implementing scripts.
URI: http://10.1.7.192:80/jspui/handle/123456789/11274
Appears in Collections:Dissertation, EC (VLSI)

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