Automation for Functional Unit Block Integration in Physical Design Layout

Abstract

In today’s world of VLSI technology, automation plays an important role for minimalizing the time, cost and human effort involved in manufacturing that product. The technology node has also decreased drastically in recent years, and this has been a challenging task in routing and DRC cleaning. To transmit the signal from one point to other or as far as possible, while minimalizing losses, is very critical in sub-micron technology. At such a stage where the dimensions are dealing in nanometer scale, the routing accuracy lowers. In this project, a similar attempt has been made for automating some tasks where lot of human effort is being invested. Also, time consumed is more as compared to the same task being performed in an automated way. The current mode of work is to do these tasks manually. Here, I have tried to perform some automation in such tasks by writing scripts in TCL in Intel’s proprietary tool meant for place and route purpose. Generally, the task of checking for DRCs and fixing them takes a lot of time. There are many DRCs that come up in a broken database or in layman terms the initial dirty database such as shorts, via-to-via, via cut-to-cut, ETE and L2L spacing violations, min length and corner length violations. All these DRCs are meant to be cleaned up before giving the layout to foundry for fabrication. These DRCs are to be cleaned up in the future prospect of this project, while in this attempt three major steps have been implemented which include reading the qbbu, which is mentioned in detail in the thesis, reading the schematic errors to check for netlist mismatch and listing the open pins and sorting the power and clock pins. The clock and the power pins are meant to be routed manually, since these nets are very time critical and need human intervention. The results are mentioned in the detailed chapters ahead which give us a picture of how the reports may differ for different scenarios. Results have been shown with taking 3 test cases as reference.