Functional Verification of Universal Memory Controller

Abstract

Increasing the performance of memory is important for increasing computer performance. With the use of a memory controller, data may be transferred between the processor and memory more effectively. In enhancing memory controller performance, a large amount of effort, resources, and time are consumed by the verification process. Developing the verification environment is a difficult task due to the difficulty in building and reusing resources, the number of protocols the verifier must understand, and the high number of iterations needed to attain full functional coverage. Verification in pre-silicon stage is considered as an important concern to avoid chip defects due to design errors, specification errors. With the increase in complexity of the design in SoC, verifying it has also become a challenging task. Verification plays a major role in verifying the design against the desired specification before tape-out. Any bugs in design not identified before tape-out will be a serious issue, hence verification is considered as a critical process in design cycle. RTL design consumes about 10 – 20% of the time in entire design cycle while Verification takes around 80 – 90% of the time. To verify universal memory controllers (UMC), this report presents an optimized generic verification environment. The UMC used for the verification supports different memories like Static Random-Access Memory (SRAM), Synchronous Dynamic Random-Access Memory (SDRAM), and FLASH with an open-source wishbone (WB) interface. This memory controller has many special features which make verification more difficult. The proposed verification methodology is configurable, scalable, reusable, and reduces the time it takes for verification to be completed. Using the test plan discussed in the report all the features of UMC have been functionally verified with 100% coverage.