Design and Implementation of UART to I2C Bridge on FPGA

Abstract

The code we write in Verilog gets translated into hardware components like gates, register, mux etc. The synthesis tool accomplishes the above task. It takes the Verilog/VHDL code and turns it to a hardware circuit which can be completely understood by the FPGA board. There are many such statement in HDL that cannot be detect by FPGA. This coding style is known as non-synthesizable coding. Synthesizable coding does mot only focuses on the functionality but also on the obtained hardware and digital elements the functionality is achieved. A communication protocol is a system of rules that allows two or more entities of a communications system to transmit information via any kind of variation of a physical quantity. The protocol defines the rules, syntax, semantics and synchronization of communication and possible error recovery methods. Protocols may be implemented by hardware, software, or a combination of both. In this Report, detailed explanation about the modules designed for the UART to I2C Bridge design. All the requirements for the necessary result and how those requirements were met are shown for each module. Each block works in a different manner and hence a unique FSM is designed for it. For the UART module a baud rate generator is necessary for synchronization of transmitter and receiver. Series In Parallel Out Register is used for UART receiver and Parallel In Series Out Register is used for Transmitter. FIFO that are used for transmitter and receiver are IPs generated in Vivado’s IP generator. The I2C master is designed in such way that it will operate according to the data received from FIFO and UART frame decoder. It will Communicate with different slaves connected to it vis I2C bus switch The I2C bus switch module between master and slave which decides to which slave the master will communicate. The I2C bus switch is a decoder which will connect the I2C master with the desired slave. The EEPROM on the FPFGA board will work as a one of the slave .The EEPROM memory will receive, store and send data as instructed by slave.