Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/11280
Title: Methodologies to Qualify Parasitic Extraction Rule-Decks
Authors: Raval, Jemin
Keywords: EC 2020
Project Report 2020
EC Project Report
EC (VLSI)
VLSI
VLSI 2020
20MEC
20MECV
20MECV11
Issue Date: 1-Jun-2022
Publisher: Institute of Technology
Series/Report no.: 20MECV11;
Abstract: PDK which is Process design kit, in IC design flow it performs very crucial tasks, and many crucial tasks are dependent on PDKs. It is like a bridge between foundry and Design Engineers. PDK contains many libraries which helps circuit designers to design circuit in very short time. It also contains different rule-decks which will be used at different steps in IC Design flows. If design and validation of all rule-decks, collaterals and EDA tools are done thoroughly, then designers can have a decent estimate of circuit performance, as well as at the fabrication stage it become easy to do fabrication of full chip, fabrication will become very easy and very rapid. Without validating collaterals in PDKs it becomes very hard for designers to design IC circuit which has same desired results after fabrication, and like these chances of chip to get fail during testing will be increased. One will be having different rule-decks and collaterals for different purpose, which are like DRC, LVS, APR tech files, Fill, RC Extraction, Libraries, Models, tools etc. this project is about Validation of Parasitic extraction decks in a PDK. Parasitic extraction deck includes technology files like ICT file, LVS files, corner definition files, layer setup files, etc. There can be some more files depending on the tool which are enabled in PDKs. In this project work is done on qualifying extraction rule decks by validating RC extraction results. To validate PDK parasitic extraction rule-decks there will be around 200+ testcases which will be used to validate these rules with the specified tool before handling PDKs to the designers. This testcase validation is done using a regression tool which help us to improve time requirement of this validation. One will be validating hundreds of testcase at the same time to achieve maximum coverage over the decks. Tests like DRC check, LVS checks, parasitic extraction, post-layout simulation, is done over this testcases. Regression tool will provide us summary report file for all the testcases, from there we can investigate based on which further improvement in PDKs are done. So, robustness of parasitic extraction rule decks are validated like this.
URI: http://10.1.7.192:80/jspui/handle/123456789/11280
Appears in Collections:Dissertation, EC (VLSI)

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