Verification of Packet Buffer Storage and Reordering in Networking IP

Abstract

In Earlier days, Silicon manufacturing cost was very high as compared to verification and testing cost. But now as the fabrication process advances, the manufacturing cost is decreased as compared to testing cost. According to Moore's law, silicon capacity continues to increase and so is the design complexity. Hence Verification efforts for such a complex design also doubled roughly every six to nine months. In today's complex design of multi-million gate ASICs, reusable IPs, and SoC Design, around 70\% of total efforts are consumed by Verification.

This thesis covers Verification Environment components using System Verilog and Universal Verification Methodology. The Packet Buffer storage and re-ordering is one block in networking IP which is responsible for storing and building the complete Ethernet packets. This block will combine the header and fetched payload and build the whole packet and then send it to the other networking blocks. It also performs reordering of fetched data. Functional coverage is written for feature of erroneous host response of Packet buffer block. Failed testcases are debugged from regressions and debugging technique is discussed. Synopsys Verdi tool is used to observe waveforms.

The UVM Register Abstraction Layer is very useful for register verification. The complete testbench example is developed for a single register verification and simulation results are shown which includes directed testcase, bit-bash sequence and functional coverage. To verify registers of packet buffer block, testcases are developed and simulation results are shown. To fix issue of register read-write using Frontdoor write and Backdoor read through testcase, register call back method is used. The complete ethernet packet flow through this packet buffer and re-order block is shown with the waveform at different interfaces by taking example of 1024B maximum read size configuration. The slicing and re-ordering logic is used to send read request to the memory and re-order the fetched data. At last, the complete Ethernet packet with header and data is shown at the output interface of the block.