Verification of IP on PCIe Protocol

Abstract

In the semiconductor industries, the planning complexity at 16 nm node and below node is exploding. Small form factor requirements and conflicting demands of high performance and low power and less area lead to the development of complex design architecture. Multi-core, multi-threading, power, performance, and area demands intensify the planning complexity and functional verification. The burden lies on functional and sequential functional domain verification to make sure that the design adheres to the specification. The biggest challenge that the semiconductor industries face is less time-to-market to deliver first pass working silicon of increasing complexity. Almost 40–50% of project resources attend functional design verification. The design verification is done at three levels of abstraction that is IP, Subsystem, and SOC level. This project deals with the verification of IP which is based on PCIe protocol. The PCIe is a 3rd generation bus that follows a serial lane-based architecture that replaces a parallel bus with a serial interconnect bus. The PCIe possesses high performance to interconnect peripheral devices and is most likely to find a place in portable devices, desktops, servers, and workstations at different computing and communication levels. PCIe incorporates a layered architecture consisting of a transaction layer, data link layer, and physical layer. The physical layer consists of two sub-blocks logical and electrical which support duplex communication. The techniques used to perform verification using the programming language System Verilog are explained. The tracker file, functional coverage, System Verilog Assertions, Checker, and UVM TB component are explained for three different features of the logical physical layer IP (LogPHY) of PCIe protocol.