Functional Verification of Mixed Signal IPs

Abstract

According to Moore’s law number of transistors placed in an integrated circuit (IC) or chip doubles approximately every two years which shows that the complexity of design is increasing rapidly. In System on Chip (SoC) environment, the whole system has integration of many working blocks, out of all these blocks if by any chance System on Chip (SoC) is not working, it would be very difficult to understand which block is not working or causing problem. To solve this kind of problem we need to verify each block before integration and so it can be less tedious to debug it at high level structure. Verification of mixed signal IPs has a different approach in comparison to fully digital design. Performing full chip verification on a mixed signal IP is a highly increasing formidable job. As the complexity is growing along with the shrinking of process nodes its now not possible to just joint together the analog and digital blocks by assuming its pre-verified individually. As for a convoluted system including a digital and analog blocks interaction can create functional errors which can further delay the tape out and results in costly re-spins. Here A mixed signal system is taken into consideration for verification, a general procedure for mixed signal verification is followed. Right from feature extraction to coverage analysis. Here a checker is formed, in high level verification internal signal are not accessible therefore functionality check is always done with equations having external signals only. Furthermore, the output from behavioral model and verification testbench environment are checked as per our requirement. According to the results we must debug the testbench as per our need. There has been used various tests cases for simulation along with that each of the test case has different sequence for power up and power down for generating different scenarios and observing the result. For a mixed signal IP two types of tests are shown here, Power awareness test and non-power awareness test. For verification of any IP or system, after writing tests and checking the functionality, generating coverage for the system is very important. From analysis of the generated coverage, functional coverage along with code coverage are obtained. The goal for coverage analysis is to try to bring statistics to 100% so that the environment can be assured to be useful at a greater extend. Uncovered signals can be observed, traced back and according to their contribution in system functionality we can exclude certain signals from coverage analysis.