Performance Power and Area Improvement in Physical Design

Abstract

Technology is advancing at a very rapid rate in every sector. Everything is getting automated. Even Integrated Circuits are becoming complex as suggested by Moore’s law. CMOS technology design node is rapidly changing due to the scaling effect. Digital circuit designs at lower technology node due to that it’s occupied less area and improvement in speed. In addition, the use of high-speed circuits or high-frequency operated devices is growing and will continue to grow in the future. Major PnR activity carried out in this project is enhancing the performance, reducing the power, optimizing the area, to meet the timing criteria and other sign-off checks at the block level. Different techniques and a couple of experiments were used at each stage to get optimised results. Partition level implementation of multi-voltage design and PnR experiments has been discussed in this project. Block has two voltage domains. CMOS devices are getting shrunk as a result, the leakage power has increased. The demand for high frequency enabled devices has resulted in increased dynamic power. If both power dissipation increases, it directly affects the overall power dissipation of the device. Various strategies are discussed in this project, swapping low threshold voltage cells into standard / high threshold voltage cells to reduce the overall power of the block. Digital design complexity is getting increased as a result, and the number of logic/functionalities also increased. More logics/functionalities to be placed in design required more area. As a part of area optimization, macro placement techniques and usage of placement blockages are discussed to overcome over utilization and congestion in design. In every PnR stage, there are various challenges faced to get optimised performance results along with optimized area and power because there is always a trade-off between performance, area and power. In this project, different techniques are discussed like reducing unnecessary clock buffers in the clock tree structure to decrease the insertion delay of the clock path and reducing the number of divergences in the clock path as a part of clock tree optimization to meet the timing. Sign-off checks results and the techniques for solving the violations are explained. All sign-off checks like IR drop check, antenna, layout vs schematic check, design rule check, voltage conformal low power check, and electrical rule check are done at block level to close the design.