Early Electromigration and IR analysis using Electrically Aware Design Methodology Baldaniya Nilesh Bhupatbhai

Abstract

The semiconductor industry faces increasing challenges in the design of complex systems-on-chip, and while some have sprung from new, only recently anticipated sources, others are, in fact, very familiar. Foremost among these are the interconnect delays caused by the increasing influence of parasitic networks. Parasitic inductance is also a growing concern. The causes of parasitic effects are well understood, as they pull upon such fundamental concepts as resistance and capacitance. However, how they are addressed at today’s level of complexity – particularly in cutting edge SoC designs – still raises many questions over methodology and how available tools should be deployed. By enabling monitoring electrical issues while creating the layout, Electrically Aware Design is used to achieve an electrically correct-by-construction layout. With this solution, it can be electrically analyzed, simulate, and verify interconnect decisions real-timeline. So, it is possible to shorten the circuit design cycle by up to 30 percent, optimize chip performance, and utilize less area.