Verification of Survivability Model

Abstract

Mostly System-on-Chips (SOCs) based design is a combination of Interconnect Protocol (IP) based design pattern, with a prominence of reuse. The expectation is that the maximum testing is performed at the Interconnect Protocol (IP) level in any System on Chip (SOC) model. Despite that, SOC-level verification is still considered as crucial and indispensable step to make sure of the quality. Modern ASIC chips are very complex and contain thousands or lakhs of transistors, thus, the probability of containing an error somewhere on the chip at the time of the design process is very likely. The earlier the error is identified, the less it will cost. Therefore, confirming the ASIC is bug free as prior as possible preferably during the design procedure is very crucial. The aim of ASIC verification is to confirm that the design meets requirements and specifications of the System. ASIC verification process is one of the important things during ASIC design process and can take almost 75-80% of the overall ASIC design and verification duration. There are multiple tools and procedures that can ease the work.

Here we are doing the verification to check the correct behavior of DUT under normal condition and also under the error condition. Some errors are injected and then checked the behavior of the DUT to make sure it works as desired. Survivability Model is a double DUT model created to verify itself for certain features.