IO Ring Checker

Abstract

Input/Output (IO) circuits enable interface between logic circuitry and the actual or raw information to be processed. They also help to isolate the integrated circuit from the unsafe, unknown and noisy environment. IOs come in many flavours and the General-Purpose IO (GPIO) is one among them. GPIOs can operate as an input, output, or a bi-directional circuit. IOs need to be protected from ESD events. One of the key ESD protection methodologies involve accurate ESD device sizing versus ESD current path distance optimization. ESD professionals have a several challenges to face as we further scale into nano-metric regime. Due to technology scaling and expansion of automated handling, failures in ICs caused by Charged Device Model (CDM) ESD are an increasingly important reliability issue. Even today, a significant portion of ESD field returns is due to damages originating from CDM stress.

Electrostatic discharge (ESD) events are recognized as a significant contributor of early life failures and failures throughout the operating life of semiconductor devices. Although contemporary integrated circuit designs include ESD protection circuitry, the effectiveness of this protection must be determined in a manner which will ensure its effectiveness in the “real world” if the part is to meet the reliability requirements for the given application. An ESD event may carry amperes of current in a short period of time, typically from hundreds of pico-seconds to hundreds of nanoseconds. Such events are very harmful for sensitive electronic components and integrated circuits (ICs). Considering ESD in IO, there are many constraints with respect to placement of cells in GPIO. Reviewing and consolidating all of them is must when it comes to designing. The task can be automated to reduce the time consumed and can increase the efficiency. IO ring checker is to build a script and automate the IO ring to include all the distance criteria, resistance limits, power supply rules and other placement rules for the successful designing of the chip. The abstract idea behind the development of the project is to satisfy the customer with all the queries faced while designing IO ring. To reduce time to response; there is a need to design such tool that the responses can be auto generated. These increases the overall time to market and time to design the IO knowing that in today’s world nothing is more precious than time.