Development of Physical Verification runsets using SVRF

Abstract

Process design kits, also known as PDKs are the bridge between the foundry and the designer. With the help of PDKs only, a designer can design, validate, test and eventually be able to fabricate the design onto actual chips. These PDKs are also an important financial source and economic asset for a foundry as to attract as many customers as possible for designing purpose. Runsets are one of the most vital part of PDKs along with many other components. Runsets basically mean the set of rules that are based on actual device and material physics, which, when obtained from the foundry, is converted to its digital form to be paired with the EDA tools which are then passed on to the customers for development of designs. Runset development requires sound knowledge of physical layout and design rules to be interpreted correctly. The development of runsets is tool specific, one such tool is the Calibre by Siemens. Calibre runsets are developed using a proprietary language known as the Standard Verification Rule Format (SVRF). Physical verification flows require a plethora of runset development and all these developments are done using SVRF at its base SVRF as a language is feature rich and provides a wide variety of commands and functions to develop highly specific algorithms and computations while forming the runsets. This project revolves around the Development of Design Rule Check (DRC) runsets, Antenna Rule check Runsets, Layout-vs-Schematic (LVS) runsets using SVRF along the concept, pre-requisites and tools of Parasitic Extraction (PEX) and represent a small but illustrative equivalent of the industry trusted standard process.