Runset Development for EDA Tools

Abstract

The Runset is part of the Process Design Kit (PDK) for the physical verification. It plays a most important role for validation. Before providing the final GDS/OASIS file to the foundry file it goes through multiple steps of verification, one of the important verifications is to validate the layout. These steps are important to ensure there are minimal number of errors while fabrication of the IC. As a part of Runset Development Team in the Internship with Intel, I got a chance to learn about different Physical Verification (PV) flows and its logic to develop the rule check for any specific Technology. In this project, it gives full details of the flow to develop and validate the Runset. It also includes detailed explanation of different physical verification flows. The overview of the different EDA tools used in this project for simulation. The description of the Rule format used in different EDA Tools is included in this report. It includes the simulation of the developed Standalone DRC, LVS, Antenna check and Extraction Runsets. The results based on the developed unit testcases developed using Calibre tool and Inverter layout design in GPDK45 library using the Virtuoso tool.