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http://10.1.7.192:80/jspui/handle/123456789/11928
Title: | Development of a tool to parse technology requirements specification document (TDR) and verify it against CAD flow implementation |
Authors: | Shekhawat, Anjali |
Keywords: | EC 2021 Project Report 2021 EC Project Report EC (VLSI) VLSI VLSI 2021 21MEC 21MECV 21MECV11 |
Issue Date: | 1-Jun-2023 |
Series/Report no.: | 21MECV11; |
Abstract: | PDK which translates to Process Design Kit. It is like a bridge between foundry and Design Engineers. It is an essential building block to enable digital, Analog and mixed signal design. It consists of number of items such as Verification decks (Design Rule Checking, Layout Versus Schematic, Antenna and Electrical rule check, Physical Extraction), Device library, Technology data (Device, Layers, layer names, layer/purpose pairs, fills), Rule files, Simulation models and more. PDK’s have evolved so that they can keep up with the increasing design complexities and rapidly growing silicon process technology. In order to keep up with the challenging requirements of industry exhaustive and efficient functionality checking of PDK’s are of prime importance. PDK contains different rule-decks, simulation models, Device Libraries, Tech files and more. These will be used at different steps in IC Design flows. If design and validation of all rule-decks, collateral’s and EDA tools are done thoroughly, then designers can have a decent estimate of circuit performance, similarly in each device library is set of rules such as spacing between two layers and other properties related to it. Without validating collateral’s in PDKs it becomes very hard for designers to design IC circuit which has same desired results after fabrication, and like these chances of chip to get fail during testing will be increased. One will be having different decks and collateral’s for different purpose, which are like DRC, LVS, Rules, RC Extraction, Libraries, Models, tools etc. There can be a bug or error while modifying these files and decks with foundry information or discussed updates. CAD engineers need to make sure all these decks do not have any bugs. Once such place where a bug can occur is translation of Technology related data to files inside the CAD flow. This Project aims to translate Technology Requirement Document which describes the valid layers, devices, physical verification rules and all the custom modifications specific to a technology node. Currently, the PDK engineer manually creates a file based on the contents of TDR which is read by the CAD flow. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/11928 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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21MECV11.pdf | 21MECV11 | 1.82 MB | Adobe PDF | ![]() View/Open |
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