Enablement of Early Parasitic Extraction and Re-simulation to reduce design Turn Around Time

Abstract

Very Large Scale Integration, as the name suggests is the process of integrating resistors, transistors, capacitors, etc. One of the processes in the VLSI Design flow is making the layout. Making a correct and accurate analog layout requires multiple iterations as parasitic estimation and post-layout simulation only happen after LVS and extraction. This post-layout simulation gives the exact functioning of the design as it considers all the parasitics (resistance and capacitance) introduced unintentionally. Due to the shrinking technology, the design rules have become more complex which again requires many iterations in the design to be up to the mark according to these rules. A good IP should meet the requirements for Electromigration, and IR drop, and thus to control the parasitics, and hence meet the EM and IR drop, requires multiple iterations of Designing-extraction-designing. This results in an increase in the efforts in layout design.

In this project, our aim would be adequate to extract the parasitics early so that we can make the changes in layout accordingly, then and there. So, we need to make the design electrically aware so that while making the layout we can counter them and keep them within the acceptable limit.

For the project we would be using Cadence Virtuoso and developing the flow, using the EAD feature. Considering some examples, we would try to compare the results like parasitic values and simulation accuracy between the traditional flow and the EAD flow. Also, we would be comparing the time taken in each flow and analyzing the reduction in the turnaround time.