Verification of Receiving Equalizer Block for Mixed Signal IP

Abstract

The Universal Serial Bus is a ubiquitous wired interconnect and has been around for almost two decades. The latest revision of the USB specification has introduced Super-Speed-Plus mode, double the rate of the existing SuperSpeed mode. Operation at this speed poses quite a few challenges in the design of the PHY layer, both in electrical and in logical sub-blocks. USB-C is the emerging standard for charging and transferring data. Right now, it’s included in devices like the newest laptops, phones, and tablets and—given time—it’ll spread to pretty much everything that currently uses the older, larger USB connector. UVM-based HVL verification environment is used for the mixed signal verification of Type-C USB PHY. Verification environment is divided into sub-level verification environments for USB 2.0 and USB 3.0 PHYs. The UVM-based HVL verification environment of the Type-C USB PHY used for digital verification has been effectively reused for the mixed-signal verification. The scoreboard and protocol checkers are enabled in mixed-signal verification. Additional tests and functional coverage were added to the existing digital environment for robust verification of the RX-EQ of mixed signal IP. The overall functional coverage is improved by merging digital regression data with mixed-signal regression data. Thus, this mixed-signal verification methodology improves the verification quality and confidence in the design. Although constrained-random stimulus generation produces many tests very quickly, results checking is needed to ensure that the design executes each test properly. Results checking can be subdivided into data checking and protocol checking. Data checking relies on the ability of the testbench to account for variability in the delay and/or order in which results come out of the design being tested. This variability is critical for covering all possible scenarios.