Design for Non-Linearity Improvement of Current Steering Digital to Analog Convertor for Biomedical Applications

Abstract

A Digital to Analog Converter find its applications in almost all the fields where the data is to be measured and to be monitored at various places /systems including human body. For biomedical portable devices which are used to measure and control parameters like ECG/EEG and in case of artificial retina implantations, there is a great demand of high-speed high-resolution Digital-to-Analog converters (DAC) designs which offers good linearity characteristics. In addition, it is expected that such design/devices dissipate minimum power. In this work mainly the focuses are given for designing current steering DAC with good linearity characteristics using different Switching devices with variety of current sources for Improving Integral and differential Non linearity characteristics. For getting the advantages of binary weighted DAC and unary weighted current DAC, the concept of segmented DAC has been adopted with various kinds of combinations. To optimize the performance in terms of linearity and power the Current Steering DACs are designed using different types of switches like NMOS, Transmission Gates and differential switches and combining the use of binary and unary weighted DACs. For all the proposed designs, the simulations are carried out in CMOS 180nm process results using standard design tools were obtained and compared with state of art results. Based on the results of the designed DACs, it can be said that segmented approach in current steering DAC with appropriate combination of no. of binary sources and no. of Unary current sources at USB side and/or LSB side play an important role in non-linearity. Differential switch offers due advantages comparted to NMOS switches and Transmission Gate switch as a switching element. The most appropriate Design of current steering DAC for biomedical application is segmented Current DAC designed DAC with differential switches. DNL and INL are 0.12 and 0.152 LSB with power consumption of 3.8uW, DNL is reduced by the factor of 7.58, INL is reduced by the factor of 8.09 and Power dissipation is increased by the factor of 2.375. Cadence virtuoso tool has been used for simulation in 180nm CMOS technology with 1.8V supply voltage.