Physical Design Implementation of an Industry Standard IP Core

Abstract

As per Moore’s law, number of transistors on a chip doubles every year while the costs are halved. For today’s ASICs, these numbers are in millions and billions. Chip design at advanced nodes pose a whole new set of challenges. The front-end is complicated by more complex device models and the back-end flow is stretched by the complex design rules. The complex rules leave limited choice for physical designers to achieve DRC clean compact routing along with timing and power budget.

Advanced nodes, complex designs and new set of design rules which are specific to electrical and manufacturing requirements demand a great degree of automation in flow, keen design knowledge and good tool expertise in physical design. Mentioned tasks must be achieved with the help of high-end EDA tools and Automated Design Flow (ADF). Moreover, as the technology node advances reliability builds the root of trust in the design which in-turn improve the quality and image of the device/company. This report has an explanation of automated design flow with each step, i.e. synthesis, floorplan, placement, clock tree synthesis, routing and fill along with various trials and results. Parasitic extraction, sign-off flows and reliability verification are also elaborated in detail.

This project aims in improving PPA (Power, Performance and Area) from Design perspective and from Tool perspective. How physical designers should change the design and select tool options for each step, in a way it will fulfill customer specs is well explained through reports and tables. Various runs have been performed and analyzed for each step, then after best one is selected for the next step. Enhancement in tool is another important part of the project, it focuses on the needs of new features in tool and how they should be verified.