Analysis of Formal Verification Methods on FPGA Products at SOC level

Abstract

This research digs into a thorough examination and evaluation of formal verification methods for FPGAs implemented at the System on Chip-SoC level. The paper analyzes the usefulness, application, and limitations of formal verification methodologies specifically adapted for SoC designs, given the rising complexity of integrated circuits and the crucial role of FPGAs in current computing systems. The main aim of this study is to check out how well different ways of making sure computer chips work right can be used for chips that are put together in a specific way. We're going to look at lots of different tools and methods to see how good they are at checking these complicated chip designs that are put together on FPGAs. Finally, this study adds to the ongoing development and refining of formal verification methods customized for FPGA-based System-on-Chip architectures. The study’s findings and conclusions aim to provide useful recommendations and considerations for practitioners and researchers working in the field of FPGA-based SoC designs and formal verification approaches