Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/12410
Title: Advancing Quality Assurance in PDK Custom Kit through the Development of a flow
Authors: Khokhara, Deep
Keywords: EC 2022
Project Report
Project Report 2022
EC Project Report
EC (VLSI)
VLSI
VLSI 2022
22MEC
22MECV
22MECV09
Issue Date: 1-Jun-2024
Publisher: Institute of Technology
Series/Report no.: 22MECV09;
Abstract: Process Design Kit is that part of VLSI industry that deals with the process technology, i.e. masking procedures of different layers present or used particularly in that technology. Design kit means, an environment or a platform that is created for the users who uses these PDK’s for developing their own designs. So, these design kits do not have any particular functionality. Rather the users which are designers of various fields use these PDK to test their design’s functionality. Also, this is important because this is the last step before the chip goes for manufacturing. Hence, it should be error free before it is being given for fabrication, else the chip will fail due to which the industries have to face huge loses. Hence PDK’s are extremely important from the industry point of view. Now, designing of these PDK’s are also done in frontend as well as in backend. In frontend the models are made and then these models are simulated using different simulators and finally they are cross checked and if discrepancies are found then they are fixed and again procedure repeats until all the discrepancies are resolved. Similarly, in backend, layouts are made for the various devices along with their test cases for the different DRC rules. These rules are validated and checked and if discrepancies are found then they are fixed and same procedure repeat itself. There are many other parameters that are to be taken care of like the LVS, DFM etc. PCell Validation also plays a significant role in PDK validation because PDK provides all tools and device libraries. Every device is simulated in order to check its working and also all the CDF parameters are verified. All the rules are specified in the DRC deck and in the format of the SVRF file. Getting basic knowledge of keywords helps in a better understanding of the verification process.
URI: http://10.1.7.192:80/jspui/handle/123456789/12410
Appears in Collections:Dissertation, EC (VLSI)

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