Improving Overall Power of a SoC Block using APR Techniques

Abstract

In any industry, technology is growing quite quickly. Automation is taking over everywhere. According to Moore's law, even Integrated Circuits are getting more complicated. The scaling effect is causing a rapid change in the CMOS technology designnode. Digital circuit designs are more efficient and faster at lower technology nodes since they take up less space. In addition, the use of fast circuits and equipment that operates at high frequencies is expanding and will do so in the future.

Physical Design is a process of transforming netlist into layout which is manufacturable [GDS]. Physical Design process is often referred as PnR (Place and Route)/ APR(Automatic Place and Route). Main steps carried out in a design is enhancing the performance, reducing the timing, and optimizing the area. During the Physical design flow design timing, constraints and power requirements should be matched and for that sign off checks will be carried out at every step. Different iterations were used at each stage to meet the requirements and performance of the block. Partition level implementation of multi-voltage design and PnR experiments has been discussed in this project.

In every PnR stage, there are various challenges faced to get optimised performance results along with optimized area and power because there is always a trade-offbetween performance, area, and power. Paper describes the optimization for PPA (Power, Performance, and area) which proposed some techniques at different stage like synthesis, floorplan, placement, and CTS. Some proposed techniques are as ungrouping hierarchy so to optimize the area and power depending on merging which can be done at synthesis stage. By lowering the number of divergences in the clock path as part of clock tree optimization to satisfy the timing requirements, as well as minimising the number of unneeded clock buffers in the clock tree structure can optimize the timing.We had done all sign off checks that needed to close the design which includes Prime time (PT), Extraction, Caliber, Voltage Conformal Low Power (VCLP), Formal Equivalence verification (FEV).