Advanced Memory BIST Implementation and validation for complex SOC Design

Abstract

This thesis project delves into the intricate realm of Memory Built-In SelfTest (MBIST) implementation and validation within the context of System-on-Chip (SoC) designs. It encompasses the meticulous insertion of memory self-test structures (SMS) into SoC designs and the thorough validation of all MBIST components integrated into the system. The seamless integration of MBIST functionality is pivotal for ensuring effective testing of memories within the broader SoC framework. The report meticulously covers the simulation aspect, with a focused emphasis on two primary types of memories: Large Arrays (Latch based memory) and Static Random Access Memories (SRAMs). Through systematic simulation of various test cases, the project endeavors to validate the robustness and reliability of the implemented MBIST solution. These simulations subject memories to diverse test scenarios to evaluate their performance, identify potential vulnerabilities, and ensure their integrity, functionality, and compatibility across different synthesis levels. At the SoC level, the report explores various testing methods aimed at guaranteeing the reliability and functionality of memory components within digital systems. Built-In Self-Test (BIST) techniques, including MBIST and Programmable Built-In Self-Test (PBIST), play a pivotal role in this process. MBIST focuses on testing embedded memory modules using predefined test patterns, while PBIST empowers users to define their test patterns, collectively aiding in fault identification and subsequent repair mechanisms. Moreover, the report delves into memory repair mechanisms, such as Built-In Soft Repair (BISR) and Built-In Hard Repair (BIHR). BISR utilizes redundancy within the memory architecture to map faulty addresses to spare rows or columns, while BIHR involves burning repair signatures into ROM-like memory, ensuring permanent repair configurations. Specialized tests like burn-in tests and retention tests further evaluate memory reliability, stability, and connectivity.