Implementation of Level Shifters Architecture

Abstract

Modern integrated circuit designs consist of several blocks, each of which may run at a different voltage for saving energy. And, at lower node technology power is very important parameter so, Low power design is the most critical issue in CMOS structure. Hence the multi- supply system is used, which is an efficient method to compress the power dissipation without lowering speed of the circuit. Voltage level shifts are necessary for communication between blocks. Apart from that this level shifter is inserted in every I/O circuit because of external voltage is different than core voltage. The level shifter (LS) circuit has become an indispensable circuit component in both analog and digital systems. The level shifters are used to change the input voltage from low to high and vice versa. To determine the optimal approach for increased performance in terms of level shifter delay, various level shifter architecture is presented in the present research. The CMOS technique is used in the design of the various level shifter circuit topologies. Comparison of three topology cross-couple, contention mitigate, and feedback level shifter are presented in this research. The development of level shifters from earlier structures are described, along with its advantages, disadvantages and comparison of power and performance.