Physical Design Implementation of Base Band Block in Sub Nanometer Technology

Abstract

In the present scenario, the VLSI industry is on the verge of reaching the maximum limit of CMOS scaling to sustain Moore’s law. Reducing the CMOS device size plays a very crucial role in the VLSI sector when prioritized aspects such as low power design, and high speed circuits or high operating frequencies are the need of the current period and will remain in the future. Baseband block is based on applications of wireless communication and consists of algorithms for modulation, demodulation, and channel coding/decoding. This is crucial in modern applications where power constraints and battery life are significant considerations. Since wireless devices depend on batteries for their device operations, there is a finite amount of battery power available to a system. Furthermore, as the chip size decreases and the complexity or features of the device increase, there is a high power consumption per chip.

Increased device scaling has led to higher static(leakage) power. To overcome such power dissipation, various low-power techniques are applied, where such dissipation can be controlled. Additionally, as devices are getting shrunk, more functions/logic are being implemented, leading to an increase in the design area. Thus, several utilization techniques are used in the design to achieve the optimal placement of logic in the design.

In every PnR stage, there are various challenges faced to get optimized performance results along with optimized area and power because there is always a trade-off between performance, area, and power. The report describes the optimization for PPA (Power, Performance, and area) using techniques such as various V T distributions, different initial utilization (such as 60%, 65%, 70%), and refining macro placement to achieve higher utilization. There are several common power management techniques like multi-threshold design, power gating, multi Vdd approach and etc that can be used in the design for power optimization. The Scope of the project also includes leakage power recovery using the signoff timing tool. While maintaining the reduced area and low power consumption results, the desired performance of the block is achieved.