Design and Functional Verification of Mixed-Signal Memory Sub-System

Abstract

As modern computer system is becoming complex day by day, system-on-chip and complex electronic circuits are making significant improvement in the semiconductor industry. This thesis dives into some of the fundamentals of designing complex SoC and how to make it more robust. This Thesis focuses on the design and integration of components such as the basic cache controller, and integrating different IPs to achieve better functionality. This thesis provides an overview of the soc design, challenges, and solutions related to integrating different IPs and designing of basic cache controller for making better memory access, reducing latency, and making a robust memory management system. It includes direct mapped cache controller design which has been designed using Verilog hardware description language. I have simulated the cache controller in modelsim tool. The design of cache controller provides insight into how write/read hit-miss operation works and how we can write it to cache memory using write-back policy. In Integration of UART into the design provides better serial communication with the CPU core. Design of UART was done in verilog hardware description language and simulated by using synopsys VCS tool. Frequency for UART was taken as 10 MHz and baud rate was 115200 bits/sec. Integration of CVA6 cpu core was done which is a open-source, high-performance RISC-V ISA based CPU core. CVA6 cpu core was integrated into design and done the setup to run basic program to make sure integration was proper. Different tools can be used to run CVA6 cpu core. In the setup of cpu core some of the simulators that we can use are verilator, synopsys VCS and Spike. In this thesis basic design cache controller and integration of IPs provide better functionality in multi design SoC.