Design of Da Based IP-Core for Half Band Filter and Polyphase Decimator

Abstract

The most common family of digital filters is made up of the finite impulse response (FIR), which is used in various applications. Digital FIR filtering is a very compute intensive operation, and since many applications require this filtering to be done in real-time, it calls for an efficient implementation of FIR filters. Distributed Arithmetic(DA) algorithm provides us a platform to implement multiply-and-accumulate function more efficiently. The architecture based on DA algorithm makes extensive use of look-up tables. It makes them ideal for implementing digital signal processing functions on FPGAs. Distributed architectures are suitable for low power portable applications, because they replace the costly multipliers with shifts and look-up tables. This work deals with DA based FIR implementation. Basic approach of distributed arithmetic algorithm is analyzed and simulated using Matlab. Timing analysis of control circuitry w. r. to input/output has been completed for Half band filter and Polyphase decimator. A common GUI is created for all programmable inputs in Matlab environment for the computation of filter coefficients, golden reference and required look up table for hardware implementation. The filter hardware implementation uses modular approach. The design is implemented using VHDL code styles and simulation is verified. The design details, its simulation, analytical evaluation and comparison with Matlab golden reference are also highlighted. Code is fully synthesizable. Chipscope testing is also carried out and results are matched with the golden references and Modelsim results.